work in progress…
Many electronic system design work involves Hardware Description Language (HDL) coding. Verilog HDL is one of the easiest HDL to learn and is the preferred language especially for entry-level engineers. This is because of its simplicity (e.g. as opposed to VHDL which is strongly typed) and its C-like syntax (which most engineering students would be familiar with).
This course is designed to provide introductory-level practical knowledge on using Verilog for simple digital logic/system design.
Upon completion of this course, the participants should be able to:
This course is designed for engineers, researchers, system designers, technical specialists, graduate students and individuals who are interested in developing fundamental skills on digital systems development, especially on FPGA platform.
Related keywords: Verilog, Digital Logic/Systems Design, HDL.
| Sessions | Details | Materials | Notes |
|---|---|---|---|
| Session 1 |
| Mainly a theoretical session (1 slot) |
|
| Session 2 & 3 |
| A more practical session (2 slots) |
|
| Session 4 & 5 |
| A more practical session (2 slots) |
|
| Session 6 | (This is optional and depends on participants' progress)
| Extra practical session (1 slot) |