Differences

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--- training:verilog_2026 [2026/04/27 03:21] – azman
+++ training:verilog_2026 [2026/04/27 03:24] (current) – azman
@@ Line 38: / Line 38: @@
 {{:archive:pgt206:verilog_p2.pdf|Slide 2}}
 </WRAP>  | <WRAP>
-Mainly a theoretical session
+Mainly a theoretical session (1 slot)
 </WRAP>  |
 ^  Session 2 & 3  | <WRAP>
@@ Line 51: / Line 51: @@
   * Sequential Logic
     * Moving towards designing a register block
+</WRAP>  | <WRAP>
+{{:archive:pgt206:verilog_p5.pdf|Slide 5}}
+</WRAP>  | <WRAP>
+A more practical session (2 slots)
+</WRAP>  |
+^  Session 6  | <WRAP>
 (This is optional and depends on participants' progress)
   * State Machines and Control Logic
     * Moving towards designing control block
 </WRAP>  | <WRAP>
-{{:archive:pgt206:verilog_p5.pdf|Slide 5}}
 {{:archive:pgt206:verilog_p6.pdf|Slide 6 (Optional)}}
 </WRAP>  | <WRAP>
-A more practical session (2 slots)
+Extra practical session (1 slot)
 </WRAP>  |