Differences

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--- training:verilog_2026 [2026/04/27 03:18] – [Who Will Benefit From This Course] azman
+++ training:verilog_2026 [2026/04/27 03:24] (current) – azman
@@ Line 17: / Line 17: @@
   - Test and verify a simple digital logic design using a Verilog compiler
-====== Who Can Benefit From This ======
+====== Who Can Benefit ======
 This course is designed for engineers, researchers, system designers, technical specialists, graduate students and individuals who are interested in developing fundamental skills on digital systems development, especially on FPGA platform.
@@ Line 38: / Line 38: @@
 {{:archive:pgt206:verilog_p2.pdf|Slide 2}}
 </WRAP>  | <WRAP>
-Mainly a theoretical session
+Mainly a theoretical session (1 slot)
 </WRAP>  |
-^  Session 2  | <WRAP>
+^  Session 2 & 3  | <WRAP>
-  * Using ModelSim
-    * Creating a new project on ModelSim
-    * Add/create Verilog files to the project
-    * Run simulation using ModelSim
-    * Analyze waveform based on simulation results
-</WRAP>  | <WRAP>
-{{:archive:pgt206:verilog_p3.pdf|Slide 3}}
-</WRAP>  | <WRAP>
-Step-by-step software session
-</WRAP>  |
-^  Session 3 & 4  | <WRAP>
   * Combinational Logic
     * Moving towards designing an ALU
@@ Line 59: / Line 48: @@
 A more practical session (2 slots)
 </WRAP>  |
-^  Session 5 & 6  | <WRAP>
+^  Session 4 & 5  | <WRAP>
   * Sequential Logic
     * Moving towards designing a register block
+</WRAP>  | <WRAP>
+{{:archive:pgt206:verilog_p5.pdf|Slide 5}}
+</WRAP>  | <WRAP>
+A more practical session (2 slots)
+</WRAP>  |
+^  Session 6  | <WRAP>
 (This is optional and depends on participants' progress)
   * State Machines and Control Logic
     * Moving towards designing control block
 </WRAP>  | <WRAP>
-{{:archive:pgt206:verilog_p5.pdf|Slide 5}}
 {{:archive:pgt206:verilog_p6.pdf|Slide 6 (Optional)}}
 </WRAP>  | <WRAP>
-A more practical session (2 slots)
+Extra practical session (1 slot)
 </WRAP>  |